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27 lines
607 B
Verilog
27 lines
607 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// The code here is used to trigger Verilator internal error
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// "InitArray on non-array"
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Jie Xu.
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typedef logic [7:0] mask_t [7:0];
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// parameter logic [7:0] IMP_MASK[7:0] = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37};
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parameter mask_t IMP_MASK = '{8'hE1, 8'h03, 8'h07, 8'h3F, 8'h33, 8'hC3, 8'hC3, 8'h37};
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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mask_t a;
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//logic [7:0] a[7:0];
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assign a = IMP_MASK;
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endmodule
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