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20 lines
412 B
Systemverilog
20 lines
412 B
Systemverilog
// DESCRIPTION: Verilator: Test of select from constant
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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sub #(.Z(0)) sub1 ();
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sub #(.Z(1)) sub2 ();
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sub #(.Z(2)) sub3 ();
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endmodule
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module sub;
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parameter Z = 0;
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wire [1:0] a = 2'b11;
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wire [0:0] b = a;
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endmodule
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