mirror of
https://github.com/verilator/verilator.git
synced 2025-01-12 17:47:34 +00:00
16 lines
357 B
Systemverilog
16 lines
357 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2019 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
// Illegal with ANSI Verilog 2001 style ports
|
|
module t
|
|
(
|
|
output bad_o_w,
|
|
output bad_o_r);
|
|
|
|
wire bad_o_w;
|
|
reg bad_o_r;
|
|
endmodule
|