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verilator/test_regress/t/t_trace_fst.out
Geza Lore dc5c259069
Improve tracing performance. (#2257) 
* Improve tracing performance.

Various tactics used to improve performance of both VCD and FST tracing:
- Both: Change tracing functions to templates to take variable widths as
  template parameters. For VCD, subsequently specialize these to the
  values used by Verilator. This avoids redundant instructions and hard
  to predict branches.
- Both: Check for value changes via direct pointer access into the
  previous signal value buffer. This eliminates a lot of simple pointer
  arithmetic instructions form the tracing code.
- Both: Verilator provides clean input, no need to mask out used bits.
- VCD: pre-compute identifier codes and use memory copy instead of
  re-computing them every time a code is emitted. This saves a lot of
  instructions and hard to predict branches. The added D-cache misses
  are cheaper than the removed branches/instructions.
- VCD: re-write the routines emitting the changes to be more efficient.
- FST: Use previous signal value buffer the same way as the VCD tracing
  code, and only call the FST API when a change is detected.

Performance as measured on SweRV EH1, with the pre-canned CoreMark
benchmark running from DCCM/ICCM, clang 6.0.0, Intel i7-3770 @ 3.40GHz,
and IO to ramdisk:

            +--------------+---------------+----------------------+
            | VCD          | FST           | FST separate thread  |
            | (--trace)    | (--trace-fst) | (--trace-fst-thread) |
------------+-----------------------------------------------------+
Before      |  30.2 s      | 121.1 s       |  69.8 s              |
============+==============+===============+======================+
After       |  24.7 s      |  45.7 s       |  32.4 s              |
------------+--------------+---------------+----------------------+
Speedup     |    22 %      |   256 %       |   215 %              |
------------+--------------+---------------+----------------------+
Rel. to VCD |     1 x      |  1.85 x       |  1.31 x              |
------------+--------------+---------------+----------------------+

In addition, FST trace size for the above reduced by 48%.
2020-04-14 00:13:10 +01:00

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$date
Sun Apr 12 20:17:58 2020
$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$var wire 5 " state $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 # cyc $end
$var logic 1 $ rstn $end
$var wire 5 " state $end
$var real_parameter 64 % fst_gparam_real $end
$var real_parameter 64 & fst_lparam_real $end
$var real 64 % fst_real $end
$var integer 32 ' fst_integer $end
$var bit 1 ( fst_bit $end
$var logic 1 ) fst_logic $end
$var int 32 * fst_int $end
$var shortint 16 + fst_shortint $end
$var longint 64 , fst_longint $end
$var byte 8 - fst_byte $end
$var parameter 32 . fst_parameter $end
$var parameter 32 / fst_lparam $end
$var supply0 1 0 fst_supply0 $end
$var supply1 1 1 fst_supply1 $end
$var tri0 1 2 fst_tri0 $end
$var tri1 1 3 fst_tri1 $end
$var tri 1 4 fst_tri $end
$var wire 1 5 fst_wire $end
$scope module test $end
$var wire 1 ! clk $end
$var wire 1 $ rstn $end
$var wire 5 " state $end
$var logic 5 6 state_w $end
$var logic 5 7 state_array(0) $end
$var logic 5 8 state_array(1) $end
$var logic 5 9 state_array(2) $end
$scope module unnamedblk2 $end
$var int 32 : i $end
$upscope $end
$scope module unnamedblk1 $end
$var int 32 ; i $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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