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36 lines
642 B
Systemverilog
36 lines
642 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for specialized type default values
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ns
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event evt;
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class Baz;
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virtual task do_something(); endtask
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endclass
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class Foo extends Baz;
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endclass
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class Bar extends Foo;
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virtual task do_something();
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@evt $display("Hello");
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endtask
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endclass
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module top();
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initial begin
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Bar bar;
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bar = new;
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fork
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#10 bar.do_something();
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#20 $display("world!");
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#10 ->evt;
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join
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end
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endmodule
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