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48 lines
940 B
Systemverilog
48 lines
940 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Member;
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rand int m_val;
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endclass
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class Cls;
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rand int m_val;
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rand Member m_member;
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function void test;
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automatic int rand_result;
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logic ok1 = 0, ok2 = 0;
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m_val = 256;
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m_member.m_val = 65535;
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for (int i = 0; i < 20; i++) begin
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rand_result = randomize();
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if (rand_result != 1) $stop;
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if (m_val != 256) ok1 = 1;
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if (m_member.m_val != 65535) ok2 = 1;
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end
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if (!ok1) $stop;
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if (!ok2) $stop;
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endfunction
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function new;
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m_member = new;
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endfunction
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endclass
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module t(/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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c.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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