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50 lines
1.0 KiB
Systemverilog
50 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Liam Braun.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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mailbox #(int) m;
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task automatic test_get;
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int v;
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m.get(v);
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// Only one thread should be here at a time (mailbox empty)
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$display("mailbox read %0t", $time);
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#1;
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m.put(v);
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endtask
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task automatic test_put;
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int v;
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m.put(42);
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// Only one thread should be here at a time (mailbox full)
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$display("mailbox write %0t", $time);
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#1;
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m.get(v);
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endtask
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initial begin
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m = new(1);
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m.put(42);
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fork
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test_get();
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test_get();
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test_get();
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join
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m = new(1);
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fork
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test_put();
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test_put();
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test_put();
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join
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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