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25f5db4b5f
Not sure why this was disabled before, but it seems legal to me to change 'forced A' -> 'B' -> 'C' into 'forced A' -> 'B', 'forced A' -> 'C' Fixes #5249
25 lines
495 B
Systemverilog
25 lines
495 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module top(input wire clk);
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logic [1:0][31:0] i;
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logic o;
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always @(posedge clk) begin
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force i = 64'hFFFFFFFF_FFFFFFFF;
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end
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sub sub_i(.i(i), .o(o));
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endmodule
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module sub (
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input logic [63:0] i,
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output logic o
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);
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assign o = |i;
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endmodule
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