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21 lines
497 B
Systemverilog
21 lines
497 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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let OFF = 4;
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let EXPECT = 16;
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let UNIQUE = 32;
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let UNIQUE0 = 64;
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let PRIORITY = 128;
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initial begin
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$assertcontrol(OFF, EXPECT);
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$assertcontrol(OFF, UNIQUE);
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$assertcontrol(OFF, UNIQUE0);
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$assertcontrol(OFF, PRIORITY);
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end
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endmodule
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