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18 lines
367 B
Systemverilog
18 lines
367 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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parameter MTM = (1:2:3);
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initial begin
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if (MTM != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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