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95 lines
2.5 KiB
Systemverilog
Executable File
95 lines
2.5 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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module t_foreach_array;
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int dyn_arr[][];
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int queue[$][$];
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int unpacked_arr [3:1][9:8];
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int associative_array_3d[string][string][string];
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int count_que;
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int exp_count_que;
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int count_dyn;
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int exp_count_dyn;
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int count_unp;
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int exp_count_unp;
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int count_assoc;
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string k1, k2, k3;
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initial begin
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// Initialize
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queue = '{'{1, 2, 3}, '{4, 5}, '{6}};
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dyn_arr = '{'{1, 2, 3}, '{4, 5, 6, 0, 10}, '{6, 7, 8, 9}};
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associative_array_3d["key1"]["subkey1"]["subsubkey1"] = 1;
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associative_array_3d["key1"]["subkey1"]["subsubkey2"] = 2;
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associative_array_3d["key1"]["subkey2"]["subsubkey1"] = 3;
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associative_array_3d["key1"]["subkey3"]["subsubkey1"] = 4;
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associative_array_3d["key1"]["subkey3"]["subsubkey2"] = 5;
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associative_array_3d["key1"]["subkey3"]["subsubkey3"] = 6;
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associative_array_3d["key2"]["subkey1"]["subsubkey1"] = 7;
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associative_array_3d["key2"]["subkey1"]["subsubkey2"] = 8;
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associative_array_3d["key2"]["subkey3"]["subsubkey1"] = 9;
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count_que = 0;
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foreach(queue[i, j]) begin
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count_que++;
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end
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exp_count_que = 0;
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foreach(queue[i]) begin
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foreach(queue[i][j]) begin
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exp_count_que++;
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end
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end
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count_dyn = 0;
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foreach(dyn_arr[i, j]) begin
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count_dyn++;
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end
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exp_count_dyn = 0;
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foreach(dyn_arr[i]) begin
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foreach(dyn_arr[i][j]) begin
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exp_count_dyn++;
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end
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end
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count_unp = 0;
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foreach(unpacked_arr[i, j]) begin
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count_unp++;
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end
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exp_count_unp = 0;
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foreach(unpacked_arr[i]) begin
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foreach(unpacked_arr[i][j]) begin
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exp_count_unp++;
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end
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end
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count_assoc = 0;
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foreach(associative_array_3d[k1, k2, k3]) begin
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count_assoc++;
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end
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if (count_que != 6 || count_que != exp_count_que) $stop;
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if (count_dyn != 12 || count_dyn != exp_count_dyn) $stop;
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if (count_unp != 6 || count_unp != exp_count_unp) $stop;
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if (count_assoc != 9) $stop;
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$write("*-* All Finished *-*\\n");
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$finish;
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end
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endmodule
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