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26 lines
524 B
Systemverilog
26 lines
524 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class C;
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task proc;
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disable fork;
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wait fork;
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endtask
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endclass
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module t;
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initial begin
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fork begin
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fork begin
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#3 $stop;
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end join_none
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#1;
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end join_none
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#2 disable fork;
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end
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initial #4 $write("*-* All Finished *-*\n");
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endmodule
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