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26 lines
907 B
Python
Executable File
26 lines
907 B
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
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test.compile(verilator_flags2=["--no-json-edit-nums", "--stats"])
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if test.vlt_all:
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test.file_grep(
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out_filename,
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r'{"type":"VAR","name":"t.f0.clock_gate.clken_latched","addr":"[^"]*","loc":"\w,44:[^"]*","dtypep":"\(\w+\)",.*"origName":"clken_latched",.*"isLatched":true,.*"dtypeName":"logic"'
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)
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test.file_grep(test.stats, r'Optimizations, Gate sigs deduped\s+(\d+)', 4)
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test.passes()
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