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ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
113 lines
3.1 KiB
Verilog
113 lines
3.1 KiB
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_mem (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk
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);
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input clk;
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output passed; reg passed; initial passed = 0;
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integer _mode; initial _mode = 0;
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reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
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reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
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reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
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reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
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reg [34:0] vec_wide;
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reg [31:0] wrd0 [15:0];
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wire [3:0] sel = 4'h3;
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wire [31:0] selout = wrd0[sel];
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// Must take LSBs into account in bit extract widths.
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wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB
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wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB
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wire [3:0] sixfrom = 13;
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wire [4:0] sixfrom2 = 16;
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wire sixtext = sixt[sixfrom];
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wire sixtext2 = sixt2[sixfrom2];
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// Non-power of 2 memory overwriting checks
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reg [2:0] np2_mem [5:0] /*verilator public*/;
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reg [2:0] np2_guard [7:6] /*verilator public*/;
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integer i;
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always @ (posedge clk) begin
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if (_mode!=0) begin
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$write("[%0t] t_mem: Running\n", $time);
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wrd0[0] = 32'h1;
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//
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for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
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mem_narrow[i] = i[7:0];
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mem_wide[i] = {i[7:0],70'hfeed};
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end
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//
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for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
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if (mem_narrow[i] !== i[7:0]) $stop;
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if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop;
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end
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//
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vec_wide <= 0;
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//
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np2_guard[6] = 0;
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np2_guard[7] = 0;
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//
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$write("selout %b %b %b\n", selout, sixtext, sixtext2);
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end
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if (_mode == 1) begin
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_mode <= 2;
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//
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i=0;
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mem_dly_narrow[0] <= ~i[7:0];
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mem_dly_wide[0] <= {~i[7:0],70'hface};
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i=1;
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mem_dly_narrow[i] <= ~i[7:0];
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mem_dly_wide[i] <= {~i[7:0],70'hface};
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//
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for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR
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// verilator lint_off width
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np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB
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// verilator lint_on width
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if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop;
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end
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// lint_checking BNDMEM OFF
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if (np2_mem[6] !== np2_mem[7]) begin
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$write("Mem[6]!=Mem[7] during randomize...\n");
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//$stop; // Random value, so this can happen
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end
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//if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's
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//
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vec_wide[32:31] <= 2'b11;
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vec_wide[34] <= 1'b1;
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$display("%x",vec_wide);
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end
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if (_mode == 2) begin
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_mode <= 3;
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//
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for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR
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if (mem_dly_narrow[i] !== ~i[7:0]) $stop;
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if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop;
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end
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//
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//$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]);
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if (vec_wide != {4'b101_1,31'd0}) $stop;
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//
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$write("[%0t] t_mem: Passed\n", $time);
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passed <= 1'b1;
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end
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_mode <= _mode + 1;
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end
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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