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40 lines
809 B
Systemverilog
40 lines
809 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t(/*AUTOARG*/);
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localparam CLOCK_CYCLE = 10;
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logic rst;
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logic clk;
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initial begin
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars;
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end
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always #(CLOCK_CYCLE/2) clk = ~clk;
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always begin
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rst = 1;
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clk = 0;
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$display("[%0t] rst: %d, rst: %d", $time, rst, rst);
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#CLOCK_CYCLE;
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rst = 0;
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$display("[%0t] rst: %d, rst: %d", $time, rst, rst);
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#CLOCK_CYCLE;
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$display("[%0t] rst: %d, rst: %d", $time, rst, rst);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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