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55 lines
1.4 KiB
C++
55 lines
1.4 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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#include <verilated.h>
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#include <verilated_vcd_c.h>
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// clang-format off
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#include VM_PREFIX_INCLUDE
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#ifdef T_TRACE_PUBLIC_SIG_VLT
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# include "Vt_trace_public_sig_vlt_t.h"
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# include "Vt_trace_public_sig_vlt_glbl.h"
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#else
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# include "Vt_trace_public_sig_t.h"
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# include "Vt_trace_public_sig_glbl.h"
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#endif
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// clang-format on
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unsigned long long main_time = 0;
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double sc_time_stamp() { return (double)main_time; }
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const unsigned long long dt_2 = 3;
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int main(int argc, char** argv) {
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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Verilated::commandArgs(argc, argv);
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VM_PREFIX* top = new VM_PREFIX{"top"};
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VerilatedVcdC* tfp = new VerilatedVcdC;
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top->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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while (main_time <= 20) {
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top->CLK = (main_time / dt_2) % 2;
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top->eval();
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top->t->glbl->GSR = (main_time < 7);
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tfp->dump((unsigned int)(main_time));
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++main_time;
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}
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tfp->close();
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top->final();
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VL_DO_DANGLING(delete top, top);
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VL_DO_DANGLING(delete tfp, tfp);
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printf("*-* All Finished *-*\n");
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return 0;
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}
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