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https://github.com/verilator/verilator.git
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46 lines
1.2 KiB
C++
46 lines
1.2 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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// Generated header
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#include "Vt_public_seq.h"
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#include "Vt_public_seq___024root.h"
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// General headers
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#include "verilated.h"
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std::unique_ptr<Vt_public_seq> topp;
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int main(int argc, char** argv) {
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vluint64_t sim_time = 1100;
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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contextp->debug(0);
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contextp->commandArgs(argc, argv);
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srand48(5);
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topp.reset(new Vt_public_seq("top"));
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topp->clk = 0;
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topp->eval();
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{ contextp->timeInc(10); }
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int cyc = 0;
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while ((contextp->time() < sim_time) && !contextp->gotFinish()) {
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if (cyc >= 5) ++topp->rootp->t__DOT__pub_byte;
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topp->eval();
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topp->clk = !topp->clk;
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topp->eval();
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contextp->timeInc(5);
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if (topp->clk) cyc++;
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}
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if (!contextp->gotFinish()) {
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vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
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}
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topp->final();
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topp.reset();
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return 0;
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}
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