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60 lines
1.6 KiB
Systemverilog
60 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic use_AnB;
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logic [1:0] active_command [8:0];
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logic [1:0] command_A [8:0];
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logic [1:0] command_B [8:0];
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logic [1:0] active_command2 [8:0];
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logic [1:0] command_A2 [7:0];
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logic [1:0] command_B2 [8:0];
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logic [1:0] active_command3 [1:0][2:0][3:0];
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logic [1:0] command_A3 [1:0][2:0][3:0];
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logic [1:0] command_B3 [1:0][2:0][3:0];
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logic [1:0] active_command4 [8:0];
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logic [1:0] command_A4 [7:0];
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logic [1:0] active_command5 [8:0];
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logic [1:0] command_A5 [7:0];
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// Single dimension assign
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assign active_command[3:0] = (use_AnB) ? command_A[7:0] : command_B[7:0];
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// Assignment of entire arrays
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assign active_command2 = (use_AnB) ? command_A2 : command_B2;
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// Multi-dimension assign
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assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0];
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// Supported: Delayed assigment with RHS Var == LHS Var
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logic [7:0] arrd [7:0];
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always_ff @(posedge clk) arrd[7:4] <= arrd[3:0];
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// Unsupported: Non-delayed assigment with RHS Var == LHS Var
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logic [7:0] arr [7:0];
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assign arr[7:4] = arr[3:0];
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// Delayed assign
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always @(posedge clk) begin
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active_command4[7:0] <= command_A4[8:0];
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end
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// Combinational assign
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always_comb begin
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active_command5[8:0] = command_A5[7:0];
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end
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endmodule : t
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