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36 lines
711 B
Systemverilog
36 lines
711 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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int m_v;
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function new(int v);
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m_v = v;
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endfunction
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extern task add_in_fork_delayed(int delay, Foo arg);
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endclass
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task automatic Foo::add_in_fork_delayed(int delay, Foo arg);
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fork
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#delay m_v = m_v + arg.m_v;
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join_none
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endtask
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module t();
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initial begin
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Foo foo1, foo2;
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foo1 = new(1);
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foo2 = new(2);
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foo1.add_in_fork_delayed(10, foo2);
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#20;
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if (foo1.m_v != 3)
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$stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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