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76 lines
1.9 KiB
Systemverilog
76 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Paul Wright.
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// SPDX-License-Identifier: CC0-1.0
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/* Working through the $time example from IEEE Std 1364-2005
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** Section 17.7.1
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** The example uses a 10ns timeunit with a 1ns timeprecision
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** For 16ns $time should return 2
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** For 32ns $time should return 3
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**/
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module t ();
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timeunit 10ns;
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timeprecision 1ns;
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longint should_be_2, should_be_3;
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real should_be_1p6, should_be_3p2;
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initial
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begin : initial_blk1
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should_be_2 = 0;
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should_be_3 = 0;
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#(16ns);
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$display("$time=%d, $realtime=%g", $time(), $realtime());
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should_be_2 = $time();
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should_be_1p6 = $realtime();
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#(16ns);
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$display("$time=%d, $realtime=%g", $time(), $realtime());
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should_be_3 = $time();
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should_be_3p2 = $realtime();
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#(16ns);
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$finish(1);
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end
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initial
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begin : initial_blk2
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#(100ns);
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$display("%%Error: We should not get here");
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$finish(1);
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end
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function bit real_chk(input real tvar, input real evar);
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begin
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real diff;
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diff = tvar - evar;
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return (diff < 1e-9) && (diff > -1e-9);
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end
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endfunction
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final
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begin : last_blk
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if (should_be_2 != 2)
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begin
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$display("%%Error: should_be_2 = %0d",
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should_be_2);
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$stop;
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end
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if (should_be_3 != 3)
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begin
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$display("%%Error: should_be_3 = %0d",
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should_be_3);
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$stop;
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end
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$display("Info: should_be_2 = %0d", should_be_2);
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$display("Info: should_be_3 = %0d", should_be_3);
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chk_2 : assert(should_be_2 == 2);
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chk_3 : assert(should_be_3 == 3);
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chk_1p6 : assert(real_chk(should_be_1p6, 1.6));
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chk_3p2 : assert(real_chk(should_be_3p2, 3.2));
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$write("*-* All Finished *-*\n");
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end
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endmodule
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