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29 lines
623 B
Systemverilog
29 lines
623 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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int m_val;
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rand int m_other_val;
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rand logic [7:0] m_pack;
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function int get_rand_mode;
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return rand_mode();
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endfunction
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endclass
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module t;
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Packet p;
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initial begin
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p = new;
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p.m_val.rand_mode(0);
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p.m_pack[0].rand_mode(0);
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$display("p.rand_mode()=%0d", p.rand_mode());
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$display(p.rand_mode(0));
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p.m_other_val.rand_mode();
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end
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endmodule
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