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52 lines
1.4 KiB
Systemverilog
52 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2024 by Antmicro. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t(/*AUTOARG*/
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// inputs
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clk
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);
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input clk;
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logic signed [31:0] in1 = 3;
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logic signed [31:0] in2 = 4;
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logic signed in_small1 = 1;
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logic signed in_small2 = -1;
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logic signed [31:0] out1;
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logic signed [31:0] out2;
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logic signed out_small1;
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logic signed out_small2;
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sub sub1(.in(in1), .in_small(in_small1), .out(out1), .out_small(out_small1));
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sub sub2(.in(in2), .in_small(in_small2), .out(out2), .out_small(out_small2));
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always_ff @(posedge clk) begin
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if (out1 == signed'(-3)
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&& out2 == signed'(-4)
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&& out_small1 == signed'(1'b1)
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&& out_small2 == signed'(1'b1)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$write("Mismatch\n");
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$stop;
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end
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end
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endmodule
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module sub(
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input logic signed [31:0] in,
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input logic signed in_small,
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output logic signed [31:0] out,
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output logic signed out_small
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); /*verilator hier_block*/
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assign out = -in;
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assign out_small = -in_small;
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endmodule
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