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66 lines
1.6 KiB
Systemverilog
66 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`ifdef VERILATOR
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`define stop $stop
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`else
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`define stop
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`endif
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`define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) !== (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0);
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module t(/*AUTOARG*/);
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int da[][2] = '{};
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int da2[][2] = '{'{1, 2}};
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int dd[][] = '{};
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int dd1[][] = '{'{1}};
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int dd2[][] = '{'{1, 2}};
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int dq[][$] = '{};
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int dq1[][$] = '{'{1}};
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int dq2[][$] = '{'{1, 2}};
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int qa[$][2] = '{};
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int qa2[$][2] = '{'{1, 2}};
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int qd[$][] = '{};
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int qd1[$][] = '{'{1}};
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int qd2[$][] = '{'{1, 2}};
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int qq[$][$] = '{};
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int qq1[$][$] = '{'{1}};
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int qq2[$][$] = '{'{1, 2}};
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initial begin
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`checkp(da, "'{}");
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`checkp(da2, "'{'{'h1, 'h2} } ");
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`checkp(dd, "'{}");
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`checkp(dd1, "'{'{'h1} } ");
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`checkp(dd2, "'{'{'h1, 'h2} } ");
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`checkp(dq, "'{}");
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`checkp(dq1, "'{'{'h1} } ");
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`checkp(dq2, "'{'{'h1, 'h2} } ");
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`checkp(qa, "'{}");
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`checkp(qa2, "'{'{'h1, 'h2} } ");
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`checkp(qd, "'{}");
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`checkp(qd1, "'{'{'h1} } ");
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`checkp(qd2, "'{'{'h1, 'h2} } ");
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`checkp(qq, "'{}");
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`checkp(qq1, "'{'{'h1} } ");
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`checkp(qq2, "'{'{'h1, 'h2} } ");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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