verilator/test_regress/t/t_timing_trace.out

$version Generated by VerilatedVcd $end
$date Tue Nov 22 16:48:14 2022 $end
$timescale 1ps $end

 $scope module TOP $end
  $scope module t $end
   $var wire 32 + CLK_HALF_PERIOD [31:0] $end
   $var wire 32 * CLK_PERIOD [31:0] $end
   $var wire  1 $ a $end
   $var wire  1 % b $end
   $var wire  1 & c $end
   $var wire  1 ) clk $end
   $var wire  1 ' d $end
   $var event  1 ( ev $end
   $var wire  1 # rst $end
  $upscope $end
 $upscope $end
$enddefinitions $end


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