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90 lines
2.5 KiB
Systemverilog
90 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Outputs
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outempty64
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);
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output [63:0] outempty64;
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parameter string OS = "O";
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parameter OI = "O"; // B is an integer of width 8
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// verilator lint_off WIDTH
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parameter string EMPTYS = "";
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parameter EMPTYI = ""; // B is an integer of width 8
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parameter bit [23:0] EMPTY24 = "";
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parameter bit [63:0] EMPTY64 = "";
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// verilator lint_on WIDTH
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parameter bit [31:0] NEST = "NEST";
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parameter bit [31:0] TEST = "TEST";
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string s;
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// verilator lint_off WIDTH
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assign outempty64 = "";
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// verilator lint_on WIDTH
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initial begin
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// IEEE: "Leading 0s are never printed" but that does not mean spaces are not
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$display(">%s< == >< (or > < also legal)", "\000");
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$display(">%s< == >< (or > < also legal)", "");
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$display(">%s< == > <", 32'h0);
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// Numeric context, so IEEE 1800-2017 11.10.3 "" is a "\000"
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if ($bits("") != 8) $stop;
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if ("" != "\000") $stop;
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if ($bits("A") != 8) $stop;
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s = "";
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if (s.len != 0) $stop;
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// IEEE 1800-2017 6.16 "\000" assigned to string is ignored
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s = "\000yo\000";
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if (s.len != 2) $stop;
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if (s != "yo") $stop;
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if ($bits(EMPTYI) != 8) $stop;
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if (EMPTYI != "\000") $stop;
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// verilator lint_off WIDTH
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if (EMPTYI == "TEST") $stop;
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if (EMPTYI == TEST) $stop;
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// verilator lint_on WIDTH
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if ($bits(EMPTY24) != 24) $stop;
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if (EMPTY24 != 0) $stop;
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$display(">%s< == > <", EMPTY24);
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if ($bits(EMPTY64) != 64) $stop;
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if (EMPTY64 != 0) $stop;
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$display(">%s< == > <", EMPTY64);
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if ($bits(EMPTYS) != 0) $stop;
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if (EMPTYS == "TEST") $stop; // Illegal in some simulators as not both strings
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if (EMPTYS == TEST) $stop;
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$display(">%s< == ><", EMPTYS);
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if ($bits(OS) != 8) $stop;
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if (OS != "O") $stop;
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if (OS == "TEST") $stop; // Illegal in some simulators as not both strings
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if (OS == TEST) $stop;
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if ($bits(OI) != 8) $stop;
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if (OI != "O") $stop;
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// verilator lint_off WIDTH
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if (OI == "TEST") $stop;
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if (OI == TEST) $stop;
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// verilator lint_on WIDTH
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if ($bits(outempty64) != 64) $stop;
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if (outempty64 != 64'h00_00_00_00_00_00_00_00) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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