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599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
8 lines
501 B
Plaintext
8 lines
501 B
Plaintext
%Warning-LATCH: t/t_lint_latch_bad_3.v:18:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value)
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: ... Suggest use of always_latch for intentional latches
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18 | always_comb
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| ^~~~~~~~~~~
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... For warning description see https://verilator.org/warn/LATCH?v=latest
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... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.
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%Error: Exiting due to
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