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22 lines
607 B
Verilog
22 lines
607 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/);
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reg [1:0] dim0;
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reg [1:0] dim1 [1:0];
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reg [1:0] dim2 [1:0][1:0];
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reg dim0nv[1:0];
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initial begin
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dim0[1][1] = 0; // Bad: Not arrayed
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dim1[1][1][1] = 0; // Bad: Not arrayed to right depth
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dim2[1][1][1] = 0; // OK
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dim2[1][1:0] = 0; // Bad: Bitsel too soon
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dim0nv[1:0] = 0; // Bad: Not vectored
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dim0nv[1][1] = 0; // Bad: Not arrayed to right depth
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end
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endmodule
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