verilator/test_regress/t/t_hier_block_trace.out

$version Generated by VerilatedVcd $end
$date Sun Nov 14 10:12:01 2021 $end
$timescale 1ps $end

 $scope module top $end
  $var wire  1 ) clk $end
  $scope module t $end
   $var wire  1 ) clk $end
   $var wire 32 + count [31:0] $end
   $var wire  8 # out0 [7:0] $end
   $var wire  8 $ out1 [7:0] $end
   $var wire  8 % out2 [7:0] $end
   $var wire  8 & out3 [7:0] $end
   $var wire  8 * out3_2 [7:0] $end
   $var wire  8 ' out5 [7:0] $end
   $var wire  8 ( out6 [7:0] $end
   $scope module i_delay0 $end
    $var wire  1 ) clk $end
    $var wire  8 & in [7:0] $end
    $var wire  8 ' out [7:0] $end
   $upscope $end
   $scope module i_delay1 $end
    $var wire  1 ) clk $end
    $var wire  8 ' in [7:0] $end
    $var wire  8 ( out [7:0] $end
   $upscope $end
   $scope module i_sub0 $end
    $var wire  1 ) clk $end
    $var wire  8 & in [7:0] $end
    $var wire  8 # out [7:0] $end
    $scope module i_sub0 $end
     $var wire  1 ) clk $end
     $var wire  8 & in [7:0] $end
     $var wire  8 # out [7:0] $end
    $upscope $end
   $upscope $end
   $scope module i_sub1 $end
    $var wire  1 ) clk $end
    $var wire  8 # in [7:0] $end
    $var wire  8 $ out [7:0] $end
   $upscope $end
   $scope module i_sub2 $end
    $var wire  1 ) clk $end
    $var wire  8 $ in [7:0] $end
    $var wire  8 % out [7:0] $end
   $upscope $end
   $scope module i_sub3 $end
    $var wire  1 ) clk $end
    $var wire  8 % in [7:0] $end
    $var wire  8 & out [7:0] $end
   $upscope $end
   $scope module i_sub3_2 $end
    $var wire  1 ) clk $end
    $var wire  8 % in [7:0] $end
    $var wire  8 * out [7:0] $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
b00000000 #
b00000000 $
b00000000 %
b00000000 &
b00000000 '
b00000000 (
0)
b00000000 *
b00000000000000000000000000000000 +
#10
b00000001 $
b00000010 %
b00000010 &
1)
b00000010 *
b00000000000000000000000000000001 +
#15
0)
#20
b00000010 #
b00000101 %
b00000011 &
1)
b00000011 *
b00000000000000000000000000000010 +
#25
0)
#30
b00000011 #
b00000011 $
b00000111 %
b00000101 &
b00000010 '
1)
b00000101 *
b00000000000000000000000000000011 +
#35
0)
#40
b00000101 #
b00000100 $
b00001000 %
b00001000 &
b00000011 '
1)
b00001000 *
b00000000000000000000000000000100 +
#45
0)
#50
b00001000 #
b00000110 $
b00001010 &
b00000101 '
1)
b00001010 *
b00000000000000000000000000000101 +
#55
0)
#60
b00001010 #
b00001001 $
b00001010 %
b00001011 &
b00001000 '
b00000010 (
1)
b00001011 *
b00000000000000000000000000000110 +
#65
0)
#70
b00001011 #
b00001011 $
b00001011 %
b00001010 '
b00000011 (
1)
b00000000000000000000000000000111 +
#75
0)
#80
b00001100 $
b00001101 %
b00001101 &
b00001011 '
b00000101 (
1)
b00001101 *
b00000000000000000000000000001000 +
#85
0)
#90
b00001101 #
b00010000 %
b00001110 &
b00001000 (
1)
b00001110 *
b00000000000000000000000000001001 +
#95
0)
#100
b00001110 #
b00001110 $
b00010010 %
b00010000 &
b00001101 '
b00001010 (
1)
b00010000 *
b00000000000000000000000000001010 +
#105
0)
#110
b00010000 #
b00001111 $
b00010011 %
b00010011 &
b00001110 '
b00001011 (
1)
b00010011 *
b00000000000000000000000000001011 +
#115
0)
#120
b00010011 #
b00010001 $
b00010101 &
b00010000 '
1)
b00010101 *
b00000000000000000000000000001100 +
#125
0)
#130
b00010101 #
b00010100 $
b00010101 %
b00010110 &
b00010011 '
b00001101 (
1)
b00010110 *
b00000000000000000000000000001101 +
#135
0)
#140
b00010110 #
b00010110 $
b00010110 %
b00010101 '
b00001110 (
1)
b00000000000000000000000000001110 +
#145
0)
#150
b00010111 $
b00011000 %
b00011000 &
b00010110 '
b00010000 (
1)
b00011000 *
b00000000000000000000000000001111 +
#155
0)
#160
b00011000 #
b00011011 %
b00011001 &
b00010011 (
1)
b00011001 *
b00000000000000000000000000010000 +
#165
0)
#170
b00011001 #
b00011001 $
b00011101 %
b00011011 &
b00011000 '
b00010101 (
1)
b00011011 *
b00000000000000000000000000010001 +