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33 lines
775 B
Systemverilog
33 lines
775 B
Systemverilog
// DESCRIPTION: Verilator: Verilog example module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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// ======================================================================
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module top
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(
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input clk,
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input fastclk,
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input reset_l,
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output wire [1:0] out_small,
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output wire [39:0] out_quad,
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output wire [69:0] out_wide,
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input [1:0] in_small,
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input [39:0] in_quad,
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input [69:0] in_wide
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);
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sub #(.TYPE_t(logic [1:0])) sub_small
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(.in(in_small),
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.out(out_small));
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sub #(.TYPE_t(logic [39:0])) sub_quad
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(.in(in_quad),
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.out(out_quad));
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sub #(.TYPE_t(logic [69:0])) sub_wide
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(.in(in_wide),
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.out(out_wide));
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endmodule
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