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14 lines
365 B
Verilog
14 lines
365 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire ok = 1'b0;
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sub sub (.ok(ok), .nc());
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endmodule
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module sub (input ok, input nc, input missing);
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initial if (ok&&nc&&missing) begin end // No unused warning
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endmodule
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