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e5b1fdf668
Squashed commit of the following: commit c1eeda7d472fc14a0ffd5c1712ae7f7c614073a1 Author: Iztok Jeras <iztok.jeras@gmail.com> Date: Tue Mar 20 16:39:44 2012 +0100 - fixed assignment operator in t_array_packed_write_read.v from = to <= - added tests for enumerations (existing tests do not use methods like next(), num(), ...) - added t_sv_bus_mux_demux test, with packed arrays, structures and unions
142 lines
5.4 KiB
Verilog
142 lines
5.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Iztok Jeras.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// parameters for array sizes
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localparam WA = 4;
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localparam WB = 6;
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localparam WC = 8;
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// 2D packed arrays
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logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array
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/* verilator lint_off LITENDIAN */
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logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array
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/* verilator lint_on LITENDIAN */
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integer cnt = 0;
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integer slc = 0; // slice type
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integer dim = 0; // dimension
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integer wdt = 0; // width
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// event counter
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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end
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// finish report
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always @ (posedge clk)
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if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// calculation of dimention sizes
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always @ (posedge clk)
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begin
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// slicing tipe counter
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case (cnt[3:2])
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2'd0 : begin slc <= 0; end // full array
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2'd1 : begin slc <= 1; end // half array
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2'd2 : begin slc <= 2; end // single array element
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default: begin slc <= 0; end
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endcase
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// dimmension counter
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case (cnt[1:0])
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2'd0 : begin dim <= 1; wdt = (slc==1) ? WA/2 : (slc==2) ? 1 : WA; end
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2'd1 : begin dim <= 2; wdt = WB; end
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2'd2 : begin dim <= 3; wdt = WC; end
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default: begin dim <= 0; wdt = 0; end
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endcase
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end
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always @ (posedge clk)
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if (cnt[30:4]==1) begin
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// big endian
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if (cnt[3:2]==0) begin
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// full array
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if ($dimensions (array_bg) != 3) $stop;
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if ($bits (array_bg) != WA*WB*WC) $stop;
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if ((dim>=1)&&(dim<=3)) begin
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if ($left (array_bg, dim) != wdt-1) $stop;
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if ($right (array_bg, dim) != 0 ) $stop;
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if ($low (array_bg, dim) != 0 ) $stop;
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if ($high (array_bg, dim) != wdt-1) $stop;
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if ($increment (array_bg, dim) != 1 ) $stop;
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if ($size (array_bg, dim) != wdt ) $stop;
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end
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end else if (cnt[3:2]==1) begin
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// half array
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if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop;
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if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop;
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if ((dim>=1)&&(dim<=3)) begin
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if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop;
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if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop;
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if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop;
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if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop;
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if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop;
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if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop;
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end
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end else if (cnt[3:2]==2) begin
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// single array element
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if ($dimensions (array_bg[0]) != 2) $stop;
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if ($bits (array_bg[0]) != WB*WC) $stop;
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if ((dim>=2)&&(dim<=3)) begin
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if ($left (array_bg[0], dim-1) != wdt-1) $stop;
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if ($right (array_bg[0], dim-1) != 0 ) $stop;
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if ($low (array_bg[0], dim-1) != 0 ) $stop;
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if ($high (array_bg[0], dim-1) != wdt-1) $stop;
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if ($increment (array_bg[0], dim-1) != 1 ) $stop;
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if ($size (array_bg[0], dim-1) != wdt ) $stop;
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end
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end
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end else if (cnt[30:4]==2) begin
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// little endian
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if (cnt[3:2]==0) begin
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// full array
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if ($dimensions (array_lt) != 3) $stop;
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if ($bits (array_lt) != WA*WB*WC) $stop;
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if ((dim>=1)&&(dim<=3)) begin
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if ($left (array_lt, dim) != 0 ) $stop;
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if ($right (array_lt, dim) != wdt-1) $stop;
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if ($low (array_lt, dim) != 0 ) $stop;
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if ($high (array_lt, dim) != wdt-1) $stop;
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if ($increment (array_lt, dim) != -1 ) $stop;
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if ($size (array_lt, dim) != wdt ) $stop;
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end
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end else if (cnt[3:2]==1) begin
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// half array
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if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop;
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if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop;
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if ((dim>=1)&&(dim<=3)) begin
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if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop;
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if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop;
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if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop;
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if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop;
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if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop;
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if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop;
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end
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end else if (cnt[3:2]==2) begin
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// single array element
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if ($dimensions (array_lt[0]) != 2) $stop;
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if ($bits (array_lt[0]) != WB*WC) $stop;
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if ((dim>=2)&&(dim<=3)) begin
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if ($left (array_lt[0], dim-1) != 0 ) $stop;
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if ($right (array_lt[0], dim-1) != wdt-1) $stop;
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if ($low (array_lt[0], dim-1) != 0 ) $stop;
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if ($high (array_lt[0], dim-1) != wdt-1) $stop;
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if ($increment (array_lt[0], dim-1) != -1 ) $stop;
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if ($size (array_lt[0], dim-1) != wdt ) $stop;
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end
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end
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end
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endmodule
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