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9d7086067c
Instead of __ALLfast.cpp and __ALLslow.cpp, we now create only a single __ALL.cpp and compile it with OPT_FAST, this speeds up small builds where the C compiler does not dominate. A separate patch will follow turning VM_PARALLEL_BUILDS on by default at a certain size. Given this change to the build there is now no point in emitting both fast and slow routines into the same .cpp file when --output-split is not set as they will be just included in the same __ALL.cpp file. To keep things simpler and the output easier to comprehend, V3EmitC has also been changed to always emit the fast and slow files separately. Also change verilated.mk to apply OPT_SLOW to all slow files, not just ones called *__Slow.cpp. This change in particular ensures __Syms.cpp is build as slow. Part of #2360.
95 lines
2.3 KiB
C++
95 lines
2.3 KiB
C++
// DESCRIPTION: Verilator: Verilog Test
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//
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// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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#include "verilatedos.h"
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#include VM_PREFIX_INCLUDE
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#include "Vt_trace_two_b.h"
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#include "verilated.h"
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#ifdef TEST_HDR_TRACE
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# ifdef TEST_FST
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# include "verilated_fst_c.h"
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# else
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# include "verilated_vcd_c.h"
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# endif
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#endif
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// Compile in place
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#include "Vt_trace_two_b.cpp"
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#include "Vt_trace_two_b__Slow.cpp"
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#include "Vt_trace_two_b__Syms.cpp"
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#include "Vt_trace_two_b__Trace.cpp"
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#include "Vt_trace_two_b__Trace__Slow.cpp"
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VM_PREFIX* ap;
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Vt_trace_two_b* bp;
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vluint64_t main_time = 0;
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double sc_time_stamp() { return main_time; }
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int main(int argc, char** argv, char** env) {
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double sim_time = 1100;
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Verilated::commandArgs(argc, argv);
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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srand48(5);
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ap = new VM_PREFIX("topa");
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bp = new Vt_trace_two_b("topb");
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#ifdef TEST_HDR_TRACE
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Verilated::traceEverOn(true);
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# ifdef TEST_FST
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VerilatedFstC* tfp = new VerilatedFstC;
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ap->trace(tfp, 99);
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bp->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.fst");
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# else
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VerilatedVcdC* tfp = new VerilatedVcdC;
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ap->trace(tfp, 99);
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bp->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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# endif
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#endif
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#ifdef TEST_HDR_TRACE
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ap->eval_step();
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bp->eval_step();
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ap->eval_end_step();
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bp->eval_end_step();
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if (tfp) tfp->dump(main_time);
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#endif
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{
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ap->clk = false;
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main_time += 10;
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}
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while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
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ap->clk = !ap->clk;
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bp->clk = ap->clk;
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ap->eval_step();
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bp->eval_step();
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ap->eval_end_step();
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bp->eval_end_step();
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#ifdef TEST_HDR_TRACE
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if (tfp) tfp->dump(main_time);
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#endif
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main_time += 5;
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}
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if (!Verilated::gotFinish()) {
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vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
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}
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ap->final();
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bp->final();
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#ifdef TEST_HDR_TRACE
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if (tfp) tfp->close();
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#endif
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VL_DO_DANGLING(delete ap, ap);
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VL_DO_DANGLING(delete bp, bp);
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exit(0L);
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}
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