verilator/test_regress
Yutetsu TAKATSUKASA d20f22beb1
Fix tristate logic when reading inout port in a module #3399 (#3523)
* Tests: Add a test to reproduce #3399

* Fix #3399. When reading an inout port in a module, it should refer the
original inout port, not the generated MODTEMP.
2022-08-07 21:12:57 +09:00
..
t Fix tristate logic when reading inout port in a module #3399 (#3523) 2022-08-07 21:12:57 +09:00
.gdbinit
.gitignore
CMakeLists.txt
driver.pl Tests: compare VCD files both ways 2022-07-27 10:48:02 +01:00
input.vc
input.xsim.vc
Makefile
Makefile_obj