mirror of
https://github.com/verilator/verilator.git
synced 2025-01-08 23:57:35 +00:00
d6ac351dcb
This switch exposes VARs, PORTs and WIREs to C++ code. It must be use with care as it has a significant performance impact and may result in mis-simulation of generated clocks. Anyhow, it is prefered over --public and useful for VPI. Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Stefan Wallentowitz <stefan@wallentowitz.de> Signed-off-by: Wilson Snyder <wsnyder@wsnyder.org>
20 lines
429 B
Plaintext
20 lines
429 B
Plaintext
The contributors listed below have certified their Verilator contributions
|
|
under the Developer Certificate of Origin
|
|
(https://developercertificate.org/).
|
|
|
|
Please see the Verilator manual for additional contributors.
|
|
|
|
Alex Chadwick
|
|
Gianfranco Costamagna
|
|
Howard Su
|
|
Jeremy Bennett
|
|
John Coiner
|
|
Kanad Kanhere
|
|
Lukasz Dalek
|
|
Maarten De Braekeleer
|
|
Philipp Wagner
|
|
Richard Myers
|
|
Sebastien Van Cauwenberghe
|
|
Stefan Wallentowitz
|
|
Wilson Snyder
|