verilator/test_regress/t/t_lint_restore_bad.out
2021-04-24 10:33:49 -04:00

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%Warning-WIDTH: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
: ... In instance t
19 | initial five = 64'h1;
| ^
... For warning description see https://verilator.org/warn/WIDTH?v=latest
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to