verilator/test_regress
Geza Lore 25f5db4b5f
DFG: Allow inlining of variabels driven from forced vars (#5259)
Not sure why this was disabled before, but it seems legal to me to
change

'forced A' -> 'B' -> 'C'

into

'forced A' -> 'B',
'forced A' -> 'C'

Fixes #5249
2024-07-13 12:35:09 +01:00
..
t DFG: Allow inlining of variabels driven from forced vars (#5259) 2024-07-13 12:35:09 +01:00
.gdbinit
.gitignore
CMakeLists.txt
driver.pl
input.vc
input.xsim.vc
Makefile
Makefile_obj