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24 lines
388 B
Verilog
24 lines
388 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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t_tri4 t_tri4 (.t4(1'b0));
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endmodule
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module t_tri4 (/*AUTOARG*/
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// Inputs
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t4
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);
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input t4;
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tri0 t4;
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initial if (t4 !== 1'b0) $stop;
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endmodule
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