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18 lines
348 B
Verilog
18 lines
348 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (/*AUTOARG*/);
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// See also t_preproc_kwd.v
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integer bit; initial bit = 1;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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