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38 lines
788 B
Systemverilog
38 lines
788 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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typedef enum bit [1:0]
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{
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E__NOT = 2'b00,
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E__VAL = 2'b11
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} E_t;
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endpackage
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module t;
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reg [1:0] ttype;
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reg m;
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enum bit [1:0] { LOCAL } l;
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always @ (m or 1'b0 or LOCAL) begin
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// Don't complain about constants in sensitivity lists
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end
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initial begin
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ttype = pkg::E__NOT;
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m = (ttype == pkg::E__VAL);
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if (m != 1'b0) $stop;
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ttype = pkg::E__VAL;
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m = (ttype == pkg::E__VAL);
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if (m != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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