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34 lines
549 B
Systemverilog
34 lines
549 B
Systemverilog
// DESCRIPTION: Verilator: Missing interface test
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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// Interface intentionally not defined
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//interface foo_intf;
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// logic a;
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//endinterface
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module foo_mod
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(
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foo_intf foo
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);
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endmodule
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module t (/*AUTOARG*/);
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foo_intf the_foo ();
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foo_mod
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foo_mod
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(
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.foo (the_foo)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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