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71 lines
1.5 KiB
Systemverilog
71 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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supply0 [1:0] low;
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supply1 [1:0] high;
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reg [7:0] isizedwire;
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reg ionewire;
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`ifdef never_just_for_verilog_mode
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wire oonewire; // From sub of t_inst_v2k__sub.v
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`endif
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wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v
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wire [1:0] tied;
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wire [3:0] tied_also;
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hello hsub (.tied_also);
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// Double underscore tests bug631
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t_inst_v2k__sub sub
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(
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// Outputs
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.osizedreg (osizedreg[7:0]),
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// verilator lint_off IMPLICIT
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.oonewire (oonewire),
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// verilator lint_on IMPLICIT
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.tied (tied[1:0]),
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// Inputs
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.isizedwire (isizedwire[7:0]),
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.ionewire (ionewire));
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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ionewire <= 1'b1;
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isizedwire <= 8'd8;
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end
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if (cyc==2) begin
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if (low != 2'b00) $stop;
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if (high != 2'b11) $stop;
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if (oonewire !== 1'b1) $stop;
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if (isizedwire !== 8'd8) $stop;
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if (tied != 2'b10) $stop;
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if (tied_also != 4'b1010) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module hello(tied_also);
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initial $write ("Hello\n");
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output reg [3:0] tied_also = 4'b1010;
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endmodule
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