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36 lines
678 B
Systemverilog
36 lines
678 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Chandan Egbert.
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// SPDX-License-Identifier: CC0-1.0
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// See bug569
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module t();
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`ifdef T_FUNC_V_NOINL
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// verilator no_inline_module
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`endif
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level1 ul1();
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initial ul1.doit(4'b0);
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endmodule
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module level1();
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`ifdef T_FUNC_V_NOINL
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// verilator no_inline_module
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`endif
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level2 ul2();
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task doit(input logic [3:0] v);
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ul2.mem = v;
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$write("*-* All Finished *-*\n");
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$finish;
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endtask
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endmodule
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module level2();
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`ifdef T_FUNC_V_NOINL
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// verilator no_inline_module
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`endif
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logic [3:0] mem;
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endmodule
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