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51 lines
1.7 KiB
Systemverilog
51 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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integer i;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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begin
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// Wildcard
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string a [*];
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int k;
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string v;
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a[32'd1234] = "fooed";
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a[4'd3] = "bared";
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i = a.num(); `checkh(i, 2);
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i = a.size(); `checkh(i, 2);
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v = a[32'd1234]; `checks(v, "fooed");
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v = a[4'd3]; `checks(v, "bared");
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i = a.exists("baz"); `checkh(i, 0);
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i = a.exists(4'd3); `checkh(i, 1);
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i = a.first(k); `checkh(i, 1); `checks(k, 4'd3);
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i = a.next(k); `checkh(i, 1); `checks(k, 32'd1234);
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i = a.next(k); `checkh(i, 0);
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i = a.last(k); `checkh(i, 1); `checks(k, 32'd1234);
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i = a.prev(k); `checkh(i, 1); `checks(k, 4'd3);
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i = a.prev(k); `checkh(i, 0);
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a.delete(4'd3);
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i = a.size(); `checkh(i, 1);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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