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22 lines
576 B
Verilog
22 lines
576 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Wilson Snyder.
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module t (/*AUTOARG*/);
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initial begin
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// verilator lint_off WIDTH
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if (32'hxxxxxxxx !== 'hx) $stop;
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if (32'hzzzzzzzz !== 'hz) $stop;
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if (32'h???????? !== 'h?) $stop;
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if (32'hxxxxxxxx !== 'dx) $stop;
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if (32'hzzzzzzzz !== 'dz) $stop;
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if (32'h???????? !== 'd?) $stop;
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// verilator lint_on WIDTH
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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