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c207e98306
What previously used to be per module static constants created in V3Table and V3Prelim are now merged globally within the whole model and emitted as part of a separate constant pool. Members of the constant pool are global variables which are declared lazily when used (similar to loose methods).
43 lines
1.4 KiB
Systemverilog
Executable File
43 lines
1.4 KiB
Systemverilog
Executable File
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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wire bit [255:0] C = {32'h1111_1111,
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32'h2222_2222,
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32'h3333_3333,
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32'h4444_4444,
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32'h5555_5555,
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32'h6666_6666,
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32'h7777_7777,
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32'h8888_8888};
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// Same values as above, but with different type
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wire logic [255:0] D = {32'h1111_1111,
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32'h2222_2222,
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32'h3333_3333,
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32'h4444_4444,
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32'h5555_5555,
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32'h6666_6666,
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32'h7777_7777,
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32'h8888_8888};
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initial begin
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// Note: Base index via $c to prevent optimizatoin by Verilator
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$display("0x%32x", C[$c(0*32)+:32]);
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$display("0x%32x", D[$c(1*32)+:32]);
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$display("0x%32x", C[$c(2*32)+:32]);
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$display("0x%32x", D[$c(3*32)+:32]);
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$display("0x%32x", C[$c(4*32)+:32]);
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$display("0x%32x", D[$c(5*32)+:32]);
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$display("0x%32x", C[$c(6*32)+:32]);
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$display("0x%32x", D[$c(7*32)+:32]);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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