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124 lines
3.2 KiB
Makefile
124 lines
3.2 KiB
Makefile
#*****************************************************************************
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#
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# DESCRIPTION: Verilator Example: Makefile for inside source directory
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#
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# This calls the object directory makefile. That allows the objects to
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# be placed in the "current directory" which simplifies the Makefile.
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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#
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#****************************************************************************/
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default: test
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# This must point to the root of the VERILATOR kit
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VERILATOR_ROOT := $(shell pwd)/..
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export VERILATOR_ROOT
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VERILATOR_NCVERILOG ?= ncverilog
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VERILATOR_VCS ?= vcs
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# Pick up PERL and other variable settings
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include $(VERILATOR_ROOT)/include/verilated.mk
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VERILATOR_SW +=
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ifeq ($(VERILATOR_NO_DEBUG),)
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VERILATOR_SW += --debug --no-dump-tree
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endif
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PERL_PACKAGES_OK := $(shell $(PERL) -e 'eval "use Bit::Vector; print 1;";')
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######################################################################
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default: test
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ifneq ($(PERL_PACKAGES_OK),1)
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test:: nopackages
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else
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ifneq ($(VCS_HOME),)
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test:: vcs
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else
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test:: novcs
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endif
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ifneq ($(NC_ROOT),)
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test:: nc
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else
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test:: nonc
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endif
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test:: vlt
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endif
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vgen.v: ./vgen.pl
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$(PERL) vgen.pl $(VGEN_FLAGS)
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# We ulimit cpu time, as some cases make gcc 3.3.4 hang
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random:
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-rm -rf obj_dir/Vgen* obj_dir/simx
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$(PERL) vgen.pl --seed=0 --numops=1000 --depth=4 --raise=4
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VERILATOR_NO_DEBUG=1 CPPFLAGS_ADD=-Wno-error VCS_HOME= NC_ROOT= bash -c "ulimit -t 120; $(MAKE) test"
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# $(MAKE) nc
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random_forever:
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while ( $(MAKE) random ) ; do \
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echo ; \
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done
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######################################################################
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nopackages:
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@echo "No perl Bit::Vector package installed."
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@echo "Not running regression test."
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novcs:
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@echo "No VCS simulator installed."
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@echo "Not running VCS regression test."
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vcs: vcs_passed.log
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simv: vgen.v sim_main.v
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vcs +cli -I +define+vcs+1 +v2k -q vgen.v sim_main.v
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vcs_passed.log : simv
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-rm -f vcs_passed.log
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./simv -l sim.log
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grep -q Finished sim.log && grep Finished sim.log > vcs_passed.log
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######################################################################
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nonc:
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@echo "No NC-Verilog simulator installed."
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@echo "Not running NC-Verilog regression test."
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nc: nc_passed.log
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nc_passed.log: vgen.v sim_main.v
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$(VERILATOR_NCVERILOG) +licqueue +define+ncverilog=1 -q vgen.v sim_main.v
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-rm -f nc_passed.log
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grep -q Finished ncverilog.log && grep Finished ncverilog.log > nc_passed.log
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######################################################################
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vlt: prep compile vlt_passed.log
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prep: vgen.v $(VERILATOR_ROOT)/bin/verilator
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$(PERL) $(VERILATOR_ROOT)/bin/verilator $(VERILATOR_SW) --cc vgen.v
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compile:
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cd obj_dir ; $(MAKE) -j 3 -f ../Makefile_obj
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vlt_passed.log vlt_run: prep compile
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-rm -f vlt_passed.log sim.log
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obj_dir/simx | tee sim.log
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grep -q Finished sim.log && grep Finished sim.log > vlt_passed.log
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######################################################################
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maintainer-copy::
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clean mostlyclean distclean maintainer-clean::
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-rm -rf obj_dir *.log *.dmp *.vpd simv* *.key vgen.v csrc INCA_libs
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