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153 lines
3.6 KiB
C++
153 lines
3.6 KiB
C++
// -*- SystemC -*-
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// DESCRIPTION: Verilator Example: Top level main for invoking SystemC model
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//
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// Copyright 2003-2015 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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//====================================================================
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#include <cstdio>
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#include <iostream>
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#include <sys/times.h>
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#include <sys/stat.h>
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#include "systemc.h" // SystemC global header
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#include "verilated_vcd_sc.h" // Tracing
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#include "Vtop.h" // Top level header, generated from verilog
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Vtop *top;
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int sc_main(int argc, char* argv[]) {
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Verilated::commandArgs(argc, argv);
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Verilated::randReset(2);
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Verilated::debug(0); // We compiled with it on for testing, turn it back off
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// General logfile
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ios::sync_with_stdio();
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// Defaults
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#if (SYSTEMC_VERSION>20011000)
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#else
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sc_time dut(1.0, sc_ns);
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sc_set_default_time_unit(dut);
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#endif
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//==========
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// Define the Clocks
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cout << "Defining Clocks\n";
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#if (SYSTEMC_VERSION>=20070314)
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sc_clock clk ("clk", 10,SC_NS, 0.5, 3,SC_NS, true);
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sc_clock fastclk ("fastclk", 2,SC_NS, 0.5, 2,SC_NS, true);
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#else
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sc_clock clk ("clk", 10, 0.5, 3, true);
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sc_clock fastclk ("fastclk", 2, 0.5, 2, true);
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#endif
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cout << "Defining Interconnect\n";
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sc_signal<bool> reset_l;
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sc_signal<bool> passed;
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sc_signal<vluint32_t> in_small;
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sc_signal<vluint64_t> in_quad;
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sc_signal<sc_bv<70> > in_wide;
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sc_signal<vluint32_t> out_small;
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sc_signal<vluint64_t> out_quad;
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sc_signal<sc_bv<70> > out_wide;
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//==========
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// Part under test
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Vtop* top = new Vtop("top");
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top->clk (clk);
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top->fastclk (fastclk);
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top->reset_l (reset_l);
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top->passed (passed);
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top->in_small (in_small);
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top->in_quad (in_quad);
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top->in_wide (in_wide);
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top->out_small (out_small);
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top->out_quad (out_quad);
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top->out_wide (out_wide);
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//==========
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// Waves
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#if VM_TRACE
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// Before any evaluation, need to know to calculate those signals only used for tracing
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Verilated::traceEverOn(true);
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#endif
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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cout <<("Test initialization...\n");
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reset_l = 1;
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#if (SYSTEMC_VERSION>=20070314)
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sc_start(1,SC_NS);
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#else
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sc_start(1);
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#endif
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//==========
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// Waves
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#if VM_TRACE
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cout << "Enabling waves...\n";
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VerilatedVcdSc* tfp = new VerilatedVcdSc;
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top->trace (tfp, 99);
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tfp->open ("vlt_dump.vcd");
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#endif
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//==========
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// Start of Test
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cout <<("Test beginning...\n");
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reset_l = 1;
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while (VL_TIME_Q() < 60 && !Verilated::gotFinish()) {
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#if VM_TRACE
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// Flush the wave files each cycle so we can immediately see the output
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// Don't do this in "real" programs, do it in an abort() handler instead
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if (tfp) tfp->flush();
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#endif
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if (VL_TIME_Q() > 10) {
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reset_l = 1; // Deassert reset
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} else if (VL_TIME_Q() > 1) {
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reset_l = 0; // Assert reset
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}
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#if (SYSTEMC_VERSION>=20070314)
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sc_start(1,SC_NS);
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#else
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sc_start(1);
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#endif
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}
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top->final();
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//==========
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// Close Waves
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#if VM_TRACE
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if (tfp) tfp->close();
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#endif
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if (!passed) {
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VL_PRINTF ("A Test failed!!\n");
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abort();
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}
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//==========
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// Coverage analysis (since test passed)
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mkdir("logs", 0777);
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#if VM_COVERAGE
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SpCoverage::write(); // Writes logs/coverage.pl
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#endif
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//==========
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// Close LogFiles
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cout << "*-* All Finished *-*\n"; // Magic if using perl's Log::Detect
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return(0);
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}
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