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49 lines
1020 B
Systemverilog
49 lines
1020 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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rand int length;
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function void test;
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automatic int rand_result, v1, v2;
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automatic string s;
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// UVM 2023 does a print, so check is ascii
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$display("get_randstate = '%s'", get_randstate());
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s = get_randstate();
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rand_result = randomize();
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if (rand_result != 1) $stop;
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v1 = length;
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set_randstate(s);
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rand_result = randomize();
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if (rand_result != 1) $stop;
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v2 = length;
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`ifdef VERILATOR // About half of the other simulators fail at this
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if (v1 != v2) $stop;
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`endif
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endfunction
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endclass
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module t(/*AUTOARG*/);
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automatic int rand_result, v1, v2;
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automatic string s;
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initial begin
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Cls c;
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c = new;
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c.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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