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28 lines
652 B
Systemverilog
28 lines
652 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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integer cyc = 0;
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// Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk
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typedef struct packed {
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logic [1024*1024:0] d;
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} s1_t; // 128 b
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s1_t biggie;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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biggie [ cyc +: 32 ] <= 32'hfeedface;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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