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12 lines
701 B
Plaintext
12 lines
701 B
Plaintext
%Warning-ASSIGNDLY: t/t_timing_net_delay.v:13:15: Unsupported: Ignoring timing control on this assignment.
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: ... In instance t
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13 | wire[3:0] #4 val1 = cyc;
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| ^
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... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
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... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
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%Warning-ASSIGNDLY: t/t_timing_net_delay.v:17:12: Unsupported: Ignoring timing control on this assignment.
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: ... In instance t
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17 | assign #4 val2 = cyc;
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| ^
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%Error: Exiting due to
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